The on-resistance of a power MOSFET (metal oxide semiconductor field effect transistor) is determined by the impurity concentration of the drift layer. If the impurity concentration is increased to reduce the on-resistance, the depletion layer does not sufficiently extend from the base layer into the drift layer. This decreases the breakdown voltage. That is, there is a tradeoff between the on-resistance and the breakdown voltage. A solution to this problem is a super junction structure in which n-pillar layers and p-pillar layers are alternately and repeatedly arranged in the horizontal direction. By achieving the balance between the amount of n-type impurity in the n-pillar layer and the amount of p-type impurity in the p-pillar layer, the super junction structure is likely to be completely depleted. Thus, a non-doped layer is artificially formed. Hence, even if the impurity concentration of each pillar layer is increased to reduce the on-resistance, the decrease of the breakdown voltage of the MOSFET can be suppressed. The power MOSFET includes a device section in which the current flows, and a termination section formed in the outer peripheral portion of the chip around the device section. By causing avalanche earlier in the device section having high avalanche withstand capability, the power MOSFET can be prevented from destruction. Also in the power MOSFET including the super junction structure, it is desired that the breakdown voltage be higher in the termination section than in the device section.